Transmission of multi-bit words typically occurs over multi-wire buses. For example, an eight-bit word may be transmitted over a bus having eight wires, one wire for each bit. But in such conventional busses, each bit carried on a given wire is independent of the remaining bits. As the data rates increase, the resulting signaling becomes problematic in that the various bits in a transmitted word become skewed from each other as the word propagates over the bus.
Given the issues with skew between multiple bits in high-speed communication, various serializer/deserializer (SerDes) systems have been developed. A SerDes transmitter serializes a multi-bit word into a serial data stream of corresponding bits. There can then be no such skew between adjacent bits on a multi-wire bus since the serial data stream is carried over a single transmission line (which may be differential). A SerDes receiver deserializes the received serial data stream into the original multi-bit word. In some SerDes systems, a clock signal is not transmitted separately from the serial data stream such that the clock signal is instead embedded in the serial data stream. A SerDes receiver for an embedded clock protocol thus includes a clock data recovery (CDR) circuit that recovers a recovered clock signal from the binary transitions in the received serial data stream. However, a CDR circuit is not limited to embedded clock systems but may be also included in SerDes receivers for source synchronous systems in which the serial data stream is transmitted in parallel with a clock signal. Although the clock signal does not need to be recovered from the data in a source synchronous protocol, a CDR circuit in a source synchronous system aligns the received clock with the serial data stream to produce a recovered clock signal so that the received data may be properly sampled responsive to the recovered clock signal.
To save power, it is conventional to periodically disable the CDR circuit. The CDR circuit thus only functions during the periods in which it is enabled. In an ideal operation, the on-time duration for the CDR circuit would depend upon the process, voltage, and temperature (PVT) corner for the corresponding integrated circuit in which the SerDes is implemented. But such PVT-aware CDR periodicity is difficult to implement and requires on-chip thermal sensors.
There is thus a need in the art for CDR circuits with reduced power consumption.